Author Topic: VHDL File for 5th sem  (Read 26740 times)

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Offline kdsingh2222

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VHDL File for 5th sem
« on: December 18, 2016, 07:31:47 pm »
VHDL file for 5th sem using Xilinx. Code, output and testbench.

1. Half Adder
2. Full Adder
3. Multiplexer
4. Decoder
5. Binary to Grey Converter
6. Parallel Adder
7. Universal Shift Register
8. D Flip flip
9. JK Flip flip
10. T Flip flip
11. SR Flip flip
12. Modulo 10 Counter
Link : https://drive.google.com/file/d/0ByuT6YxSHYuTcXNQS0REOGtMSW8/view?usp=sharing
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